Austin TX - Sr. Verification Design Engineer - Ref: 940004

Job description

Experience with modeling (TLM), Block- and Top-Level ASIC and SoC verification, test bench development, HW emulation, HW acceleration, SW driven verification.

Required competence

ASIC, SoC or FPGA RTL verification with a minimum of 10 years of work experience debugging RTL at the block and/or top-level with hands-on verification utilizing System Verilog/UVM.

Developing test plans and directed/randomized test cases from scratch Transaction Level Modeling (TLM) experience with System C.

Wanted competence

On -Site work only.

Place of assignment

Austin TX

Assignment duration

Start: 2019-04-15
End: 2019-08-15

If this sounds interesting, please send your CV (in MS Word) and some lines on how you meet the requirements and will contribute to this position, as soon as possible, no later than 2019-04-30.

Contact person

Paul Barone
+1 214 402 8682


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